Flash electrically programmable read only memories ("EPROMs") and flash electrically erasable and programmable read only memories ("EEPROMs") are solid state devices that can persistently store digital data. As shown by FIG. 1, an EPROM-type flash cell 10 typically has a metal-on-silicon ("MOS") structure that includes a substrate 12, source and drain regions 14, 16, a floating gate 18 overlying MOS channel region 20 but separated therefrom by a thin layer region 22 of oxide 24. A control gate 26 is formed overlying floating gate 18. For a flash EPROM, it is necessary to surround the source region with a lightly doped region 15 of like-conductivity type dopant. The substrate or bulk 12 is tied to a potential Vbb that typically is ground. For the NMOS device depicted, substrate 12 is doped with P-type impurities, and the source and drain regions are doped with N-type impurities. For a flash EPROM, N+ source region 14 is surrounded by an N- region 15. The N- region 15 is included to protect the source junction from the large source-floating gate electric field used to electrically erase the cell. But for the presence of this N- region, the magnitude of the electric field during erase operations could damage the source region.
Of course a PMOS device may be formed by substituting an N-type substrate, and P-type source, drain regions. Generally, NMOS devices are preferred to PMOS devices in that the majority carriers in NMOS devices, electrons, have 2.5 times the mobility of the majority carriers, holes, in PMOS devices, and thus can operate more rapidly. Although a flash-type EPROM cell is depicted, it is to be understood that the present invention may also be used with EPROM, or EEPROM type memory as well.
A Vcg voltage coupled to control gate 26 can affect charge stored on floating gate 18, which charge affects the Vt threshold voltage of MOS device 10. The magnitude of charge on the floating gate controls the minimum (or Vt) voltage Vcg that will turn-on device 10, causing drain-source current to flow across the channel region 20. Device 10 is programmed to one of two states by accelerating electrons from substrate channel region 20 through the thin gate dielectric 22 region onto floating gate 18.
The state of device 10, e.g., how much charge is stored on floating gate 18, is read by coupling an operating voltage Vgs across source and drain regions 14, 16, and then reading the drain-source current Ids to determine whether the device is ON or OFF for a given control voltage level Vcg.
To program a flash EPROM (or to erase a flash EEPROM, whose definitions of erasing and programming are opposite) it is necessary to apply a positive high voltage Vcg, e.g., perhaps +10 VDC to control gate 26, while applying perhaps +5 VDC to drain 16, and 0 VDC to source 14. As hot electrons are accelerated and travel from source to drain, the electric field created by the high Vgs and Vds voltages can pull some hot electrons from the drain to the floating gate. (No electrons will be pulled to the floating gate from the source, which is at ground potential.)
On the other hand, to erase a flash EPROM (or to program a flash EEPROM), it is necessary to apply a negative high voltage Vcg, e.g., perhaps -10 VDC, and a positive Vs or perhaps +5 VDC, while allowing Vd to float. The negative Vcg high voltage and Vs produce a large tunnel electric field that can push electrons from the floating gate 18 to the source 14. (No electrons are pulled out of the floating gate to the drain, as the floating drain will not generate a large electric field.) Although one can erase a flash EPROM by providing positive high voltage to the source and grounding the control gate, so doing increases source region junction leak current, and increases hot-hole injection at the source region. Unfortunately, this causes hole trapping, and degrades the storage capability and endurance of the memory cell.
Typically the circuitry with which memory cells 10 are used is powered by a single low voltage power supply, a 3.3 VDC battery for example, although batteries ranging from perhaps 1.2 VDC to 5 VDC or higher may instead be used. As will be described, positive and negative high voltage pump circuits are commonly used to generate the +10 V or so high voltage necessary to program and erase memory cells from a single lower voltage power supply.
As shown in FIG. 2, it is common to form an integrated circuit ("IC") 100 that includes a plurality of cells 10 that are arrayed in addressable rows and columns that define a storage array 110. Address logic 120 permits accessing a specific cell in such an array. For example, during a program/read or erase operation, a given cell 10 may be accessed by applying the proper Vgs, Vd, Vs potentials to all cells in a column containing the addressed cell, and to the row containing the addressed cell. For ease of illustration, address logic 120 is shown as having a single output lead, but in practice there will be multiple output leads, including leads for Vgs, Vd, and Vs.
As shown in FIG. 2, IC 100 preferably operates from a single low voltage power supply Vdd, which may be a battery if, for example, IC 100 is a storage unit within a laptop computer. Typically the low voltage power supply magnitude is 5 VDC, although the trend has been toward lower voltage magnitudes, e.g., 3.3 VDC or 2.5 VDC, with a goal of perhaps 1.2 VDC.
To generate the high voltage necessary to program or erase the various cells, IC 100 will include a positive high voltage pump circuit 130 that outputs a high positive potential V.sub.Pp, and a negative high voltage pump circuit 140 that outputs a high negative potential V.sub.Pn. IC 100 also includes a phase generator circuit 150 that outputs a plurality of non-overlapping different phase pulse trains that drive the positive and negative pump circuits. Many prior art high voltage pump circuits require phase generators that provide four-phase output pulse trains, denoted .o slashed., .o slashed.2, .o slashed.3, .o slashed.4.
Understandably the necessity to fabricate both positive and negative pump circuits on IC 100 requires IC chip area that might otherwise be available for other circuitry, more memory cells for example. Also, if phase generator 150 must output many multiply-phased non-overlapping pulse train signals, the phase generator circuitry may be complex will consume IC chip-area. Further, as more phases are required to be generated, the practical upper frequency of the phase generator output signals decreases, due to the necessity that the various phase signals not overlap each other at their voltage transitions.
FIG. 3A depicts a prior art five-stage positive high voltage so-called Dickson charge pump, such as might be used for circuit 130. Details of this configuration may be found in "On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique", Dickson, J., IEEE J. Solid State Circuits, vol. 11, pp. 374-378, June 1976. In this configuration, a plurality of voltage pump or multiplier or rectifier stages is formed, each comprising an NMOS used as a diode, and an associated charging capacitor. Each NMOS transistor has its gate and source leads coupled together, with the result that Vgs=0 VDC. The substrate or bulk potential Vbb is typically ground, or 0 VDC, to prevent the P-substrate, N-source/drain regions from becoming a current conducting forward-biased PN junction. The gate-source of M0 may be said to define the anode node for the string of rectifier stages, and the drain of M5 may be said to define the cathode node for the string of rectifier stages. In FIG. 3A, the anode node is coupled to the low voltage power supply Vdd.
In the configuration shown, two-phase non-overlapping pulse trains .o slashed.1, .o slashed.2 are provided, for example from a phase generator 150. By non-overlapping it is meant that 0 to 1, and 1 to 0 voltage transitions of one phase never overlap with transitions of the other phase, although duty cycle of the two phases is not critical. As shown in FIG. 3A, each waveform has a 0 to 1 voltage differential E1 that typically is equal to Vdd. Assume that Vdd=E1=3.3 VDC.
FIG. 3B shows the equivalent circuit of FIG. 3A, such that the leftmost transistor M0 in FIG. 3A corresponds to equivalent diode D0 in FIG. 3B, M1 corresponds to D1, and so on. In FIG. 3B, assume that node A is initially at (Vdd-Vt) or about (3.3-1)=2.3 VDC potential, where Vt is the equivalent diode voltage drop, where Vt here is assumed to be about 1 VDC.
In reality, the "diode drop" will be a Vt threshold voltage drop of perhaps 1 VDC for the NMOS transistors used in the circuit. This Vt drop will always be present because the gate potential can never be more positive than the source potential (since Vgs=0). In stating that Vt.apprxeq.1 V, a simplifying assumption is made that no MOS body effect is present. In practice, Vt may be 2 V or so rather than 1 V, due to body effect induced by higher pumped voltages with respect to ground potential. Thus, where Vt.apprxeq.1 V is assumed, it must be remembered that body effect contributions are not being accounted for.
The rising edge of waveform .o slashed.1 AC-couples through capacitor C1 to superimpose a positive transition of magnitude E1 (e.g., +3.3 VDC) upon the 2.3 VDC potential, raising node A to a peak voltage of +5.6 V. Node B will follow the potential at node A less a D1 diode drop of 1 VDC, and will see (5.6-1)=4.6 VDC. However the positive-going transition of the .o slashed.2 waveform AC-couples through capacitor C2 to initially superimpose an E1=3.3 V transition upon node B, increasing the peak node potential to (4.6+3.3)=7.9 VDC.
Node C will follow this potential, less a 1 VDC D2 diode voltage drop, which puts the peak node C potential at 6.9 VDC. However, the positive-going transition of the .o slashed.1 waveform AC-couples through capacitor C3, increasing the node C potential by 3.3 V to (6.9+3.3)=10.2 VDC. Similarly, in this example, node D will follow this potential less a D3 diode voltage drop, and will be 9.2 VDC, until the positive-going transition of the .o slashed.2 waveform AC-couples through capacitor C4 to increase the potential to 12.5 VDC peak. Waveform E will be one diode D4 voltage drop lower, or 11.5 VDC, until the positive-going transition of .o slashed.1 increases the potential to 14.8 VDC. The peak positive output voltage V.sub.Pp at node F will be one diode D5 voltage drop lower, or about +13.8 VDC.
Of course, the above description neglects body effect in the various transistors, and results in too high an output voltage V.sub.Pp. More realistically, if a Vt.apprxeq.2 V (rather than 1 V) is assumed to better account for body effects, V.sub.Pp at node F in FIG. 3B will be closer to about +7.8 VDC, rather than +13.8 VDC. In reality, each of M0, M1, M2, M3, M4 and M5 can have a different Vt value. For example, M0 will experience the smallest body effect contribution and will exhibit the smallest Vt, perhaps about 1 V. M5, on the other hand, sees the largest potentials and will experience the largest body effect contribution, and will exhibit the largest Vt, perhaps about 2 V. Depending upon MOS fabrication process variations, the V.sub.Pp output from FIG. 3A will range from about 7.8 VDC upward to but not exceeding about 13.8 VDC.
In the configuration of FIG. 3B, Typically the various capacitors coupling capacitors C1-C5 are in the 10-20 pF range, depending upon the driving current requirements and magnitude of load capacitor C.sub.LOAD, which will be substantially larger, perhaps in the 1000 pF range.
Although the Dickson configuration of FIG. 3A works, it is not very efficient because of the diode drop associated with each stage. More stages may be added to boost the output voltage even higher, but on a relative basis even coupling capacitors in the 2 pF to 10 pF range require not insubstantial IC chip area.
FIG. 3C shows a four-phase prior art four-stage negative high voltage charge pump, such as might be used for circuit 140, as disclosed in U.S. Pat. No. 5,077,691 to Haddad et al. Series-coupled PMOS transistors M0, M1, M2, M3, and M4 associated charge capacitors form a plurality of voltage rectifier stages. Together, capacitor C1 and PMOS M1 comprise a first pumping stage, capacitor C2 and PMOS C2 comprise a second pumping stage, and so-on. FIG. 3C is typical of prior art negative high voltage generators in that PMOS transistors are employed. Understandably, however, NMOS transistors would be preferred to PMOS devices because of the higher mobility associated with electrons in NMOS transistors.
One interesting aspect of this configuration is that charge-switching transistors M0A, M1A, M2A, M3A, and M4A and associated capacitors C1A, C2A . . . C5A, essentially eliminate the Vt threshold drop otherwise present in the associated string of series-coupled PMOS transistors. In essence, the charge-switching transistors can couple the gate and source leads of the associated series-coupled PMOS transistors, without imposing a Vgs=0 condition as in FIG. 3A. The result is that the gate potential of the series-coupled PMOS transistors can float at a potential several volts more negative than the source lead potential. The result is that the full E1 magnitude potential swing of the phase pulse trains can be coupled from drain-to-source across each series-coupled PMOS transistor, without incurring a Vt loss. In the following example, assume that Vdd=E1=3.3 VDC.
The Vt cancelling aspect of the Haddad et al. circuit is achieved as follows. The rising edge of waveform .o slashed.3 is AC-coupled via capacitor C1 to the gate of transistor MOA, where the gate voltage will initially be clamped to about .vertline.1V.vertline. of PMOS threshold voltage Vtp. But the falling edge of waveform .o slashed.1 AC-couples a transient to the gate of M0 of E1.apprxeq.Vdd.apprxeq.3.3 V. This -3.3 V gate voltage permits M0 to pass a potential at virtual ground from its source-to-drain to the gate of M0A without a .vertline.Vtp.vertline. threshold voltage drop (typically.apprxeq.1 V). When the falling edge of .o slashed.3 AC-couples to the gate of M0A, a peak negative voltage of about -3.3 V is achieved at the upper end of C1A. In similar fashion, the following three stages (C2, C3, C4 and associated transistors) multiply the negative potential. Assuming that body effect may be neglected, approximately -(4).times.(3.3V)+Vt=-(13.2+1) or 12.2 VDC appears across C.sub.LOAD. The +1 V Vt offset accounts for the initial gate potential at M0 being approximately +1 VDC rather than ground.
The advantage of the PMOS configuration of FIG. 3C is that voltage multiplication efficiency is high relative to the configuration of FIG. 3A. In FIG. 3C, if E1 is 3.3 V, and there are 5 rectification stages, the peak negative output voltage V.sub.Pn will be approximately -(5).times.(3.3 V)+1 V.apprxeq.-15.5 V. Again, this magnitude of V.sub.Pn is optimistic in that body effects have not been fully accounted for.
While eliminating Vt improves charge pump efficiency, unfortunately the Haddad et al. circuit requires four non-overlapping phase signals, .o slashed.1, .o slashed.2, .o slashed.3, .o slashed.4, such as shown in FIGS. 3D-3G. As noted, having to output four non-overlapping phase signals adds design complexity to phase generator 150, requires additional IC chip area to implement, and reduces the frequency of each phase signal. For example, the two-phase configuration of FIG. 3A may utilize a phase signal having perhaps a 5 MHz repetition rate. By contrast, the configuration of FIG. 3C will have to utilize phase signals having substantially lower repetition rates, assuming that the phase generator 150 in each instance is functioning at maximum frequency without phase overlap. Thus, the two-phase configuration of FIG. 3A can pump substantially faster than the four-phase configuration of FIG. 3C, and will exhibit improved pump performance.
Neither prior art FIG. 3A nor 3C provides for discharging the capacitor-MOS interconnection nodes, or for precharging these nodes. Discharging, if implemented, can be advantageous in permitting the capacitor node voltage to be reset. On the other hand, precharging, if implemented, could allow the circuits to more rapidly achieve a steady-state high voltage output. Further, neither of these circuits takes special care to protect the MOS substrate from undesired high voltage conditions. Such conditions can give rise to leakage currents and/or damage to the MOS transistors.
With respect to FIG. 2, it will be appreciated that there is a need for a single high voltage pump circuit that could output positive high voltage or negative high voltage. Such a circuit would save considerable IC chip area. Further, such a positive/negative high voltage pump circuit should operate with fewer than four phases, to simply design of the phase generator, thus saving additional IC chip area and permitting faster repetition rate phase signals. Such a positive/negative high voltage pump circuit should provide an option for cancelling Vt voltage drops, to promote efficiency, preferably using less than four phases. Further, such a pump circuit should provide an option for precharging or discharge capacitor voltage nodes, and for protecting the MOS substrates.
In summary, what is needed is a pump circuit that can rapidly boost low voltage Vdd to high positive or negative voltage, using the least number of charge pump stages, while utilizing relatively small IC chip area. Preferably such circuit should permit implementing precharge and discharge of capacitor nodes, and should provide protection for the substrates of MOS devices used to implement the circuit.
The present invention discloses such a positive/negative high voltage charge pump circuit.